Flash electrically programmable read only memories ("EPROMs") and flash electrically erasable and programmable read only memories ("EEPROMs") are solid state devices that can persistently store digital data.
Flash memory has grown substantially in popularity for storing programs and data due to its ability to re-program data that can be stored in non-volatile fashion. Industrial applications find flash memory frequently used in embedded applications such as microprocessors that can store boot code or house-keeping parameters. Formerly such applications were largely reserved for EPROM devices, but more recently, the market is moving to flash memories. Non-memory system circuits are largely implemented using complementary metal-oxide semiconductor ("CMOS") circuitry, which advantageously operates from low voltage of perhaps 5V or less.
As shown by FIG. 1, an EPROM-type flash cell 10 typically has a metal-on-silicon ("MOS") structure that includes a substrate 12, asymmetrical source and drain regions 14, 16, a floating gate 18 overlying MOS channel region 20 but separated therefrom by a thin layer region 22 of oxide 24. A control gate 26 is formed overlying floating gate 18. For a flash EPROM, it is necessary to surround the source region with a lightly doped region 15 of like-conductivity type dopant. The substrate or bulk 12 is tied to a potential Vbb that typically is ground.
For the NMOS device depicted, substrate 12 is doped with P-type impurities, and the source and drain regions are doped with N-type impurities. For a flash EPROM, N+ source region 14 is surrounded by an N- region 15 to protect the source junction from the large source-floating gate electric field used to electrically erase the cell. (Further details of this Fowler-Nordheim source-region tunneling erase mechanism is described later herein.) This N- region helps reduce electric field magnitude between source nodes and the first polysilicon layer ("poly1, not shown) during erase operations. (By contrast, channel-hot-electron injection programming occurs from the drain region, as described later herein.) In any event, prior art cell 10 will have asymmetrical drain and source regions. In addition to adding to fabrication costs, the asymmetry means that functionally the source and drain regions may not be used interchangeably. (Of course by reversing dopant types, a PMOS device could instead be implemented.)
It has long been recognized that programming efficiency of flash memory cells gradually decreases with increasing erase/program cycles. As the number of erase/program cycles exceeds a limitation, cell 10 will typically fail during programming within a predetermined time. The failure number of erase/program cycles is termed the cell's endurance. While endurance limitations are relatively unimportant for one tine programming applications, endurance is a critical concern for re-programmable flash applications, e.g., flash memory used as an EPROM replacement.
Flash memory cell decrease in programming efficiency is believed due to trapping of holes in the thin tunnel oxide that separates the cell substrate from the floating gate. During programming, hot holes are injected from the drain region into the floating gate. But holes that do not receive sufficient momentum can become trapped in the tunnel oxide where they degrade oxide electric fields. As a result, programming efficiency decreases as more and more holes become trapped with increasing numbers of program cycles, with degradation of the cell storage capability, and endurance.
Unfortunately, as described herein, programming conventional flash memory cells such as cell 10 can only be accomplished on the drain region side because the source-drain topography is not symmetrical. Thus, the asymmetrical drain-source regions found in prior art cells precludes interchanging the drain and source functions after substantial hole trapping has occurred, to extend the cell's endurance.
A Vcg voltage coupled to control gate 26 can affect charge stored on floating gate 18, which charge affects the Vt threshold voltage of MOS device 10. The magnitude of charge on the floating gate controls the minimum (or Vt) voltage Vcg that will turn-on device 10, causing drain-source current to flow across the channel region 20. Device 10 is programmed to one of two states by accelerating electrons from substrate channel region 20 through the thin gate dielectric 22 region onto floating gate 18. Because they can only store "0" and "1" data states, such cells are termed binary. Understandably, if it were possible to store more than two data states, a memory array of a given storage capacity could be implemented using fewer cells, or for a given IC chip area, increased storage capacity could be implemented.
The state of device 10, e.g., how much charge is stored on floating gate 18, is read by coupling an operating voltage Vds across source and drain regions 14, 16. The drain-source current Ids is then read to determine whether data stored in the device is a logic level one or zero for a given control voltage level Vcg. Conventional memory cells store only two logic states ("1" and "0"), which may be differentiated by sensing relative current levels, e.g., perhaps 100 .mu.A versus 10 .mu.A.
In prior art flash and EPROM memory, a data "1" state results when flash cell threshold potential (Vt) is lowered to define a "low Vt", whereas a data "0" results when cell threshold voltage is increased to define a "high Vt". Table 1, below, depicts the potentials or exposure to ultraviolet ("UV") commonly used to alter Vt in conventional flash or EPROM memory cells.
TABLE 1 ______________________________________ stored data state Flash EPROM ______________________________________ 0 Vt &gt; 6.5 V Vt &gt; 6.5 V (after program) 1 Vt &lt; 3.0 V Vt &lt; 1.2 V (after UV erasure) ______________________________________
Although UV erasure has been used for many years, it has associated disadvantages. UV-erasure requires that the memory package include a UV-transparent window through which UV may pass to influence the floating gate. Thus, packaging costs for a UV-erasable memory are increased if the memory is to be re-programmable multiple times. As memory density increases, cell size decreases and it becomes more difficult to effectively erase smaller sized floating gates within a given time interval. Further, UV-erasure is a slow process, requiring perhaps 20 minutes.
Flash memory may be erased by UV (in which case Vt will be reduced to about &lt;2V) or it may be erased electronically (in which case Vt will be reduced to about &lt;3V). EPROM memory may only be erased by UV, in which case Vt will be reduced to about &lt;1.2V. EPROM UV-erased Vt differs from flash UV-erased Vt because EPROM has a higher coupling ratio (e.g., 0.7 compared to 0.5). As described later herein, coupling ratio refers to the effectiveness of voltage transfer from a control gate to a floating gate node.
Two mechanisms are in common use to program a flash EPROM (or to erase a flash EEPROM, whose definitions of erasing and programming are opposite), namely channel-hot-electron ("CHE") injection, and Fowler-Nordheim ("FN") tunnelling. Commonly, EPROM-flash devices use FN-erase mode and CHE-program mode operations, which combination is sometimes referred to as ETOX, for EPROM tunnel oxide technology. On the other hand, EEPROM-flash devices commonly use FN-erase mode, and FN-program mode operations.
Table 2, below, summarizes prior art mechanisms and voltages for erasing and programming conventional memory cells. In Table 2, F-N denotes Fowler-Nordheim tunnelling mechanism, CHE denotes channel hot electron injection mechanism, LC denotes low current, MC denotes medium current, and HV denotes high voltage.
TABLE 2 ______________________________________ CONFIGU- RATION ERASE mode PROGRAM mode ______________________________________ prior art F-N - LC Vt CHE - HC Vt 1 & HV decreases & HV increases &lt;10 nA, 0.5 mA, .+-.10 V .+-.10 V prior art F-N - LC Vt FN - LC Vt 2 & HV increases & HV decreases &lt;10 nA, &lt;10 nA, .+-.15 V .+-.10 V ______________________________________
Thus, programming prior art memory cells involves increasing Vt such that the state of data stored in the cell changes from 1 to 0, while erasing involves decreasing Vt to change a stored 0 to a 1. As noted above, however, generally F-N tunneling requires higher voltages than CHE injection, which higher potentials can substantially limit memory cell device scaling.
For prior art EPROM-flash cell 10 in FIG. 1, CHE injection programs the cell to an off-state in read mode, by applying high voltage Vcg of perhaps +10V to control gate 26, while applying perhaps +5V to drain 16, and 0V to source 14. The high potential accelerates hot electrons that travel from source to drain, and the electric field created by high voltages Vgs and Vds can pull some hot electrons from the drain to the floating gate. (No electrons will be pulled to the floating gate from the source, which is at ground potential.) When using CHE injection, the drain-source channel current will be approximately 0.5 mA/cell.
If prior art EPROM-flash cell 10 is erased using FN, perhaps -10V is coupled to control gate 26, +5V is coupled to the source, and the drain floats. FN-mode erasing can be accomplished with a tunnel current of approximately 10 nA/cell. (Although one can erase an EPROM-flash cell by providing positive high voltage to the source and grounding the control gate, so doing increases source region junction leak current, and increases hot-hole injection at the source region.)
In the prior art, programming an EEPROM-flash cell using FN technology requires applying approximately -10V to control gate 26, applying +5V to source 14, and floating drain 16. The negative high voltage Vcg and Vs produce a large tunnel electric field that can push electrons from the floating gate 18. to the source 14. (No electrons are pulled out of the floating gate to the drain, as the floating drain will not generate a large electric field.) Unfortunately, this causes hole trapping, and degrades the storage capability and endurance of the memory cell.
To erase an EEPROM cell using FN technology, approximately +15V is applied to control gate 26, while drain 16 and source 14 are grounded. As was the case for an EPROM-flash cell, FN erasing can be accomplished with a tunnel current of approximately 10 nA/cell.
It will be appreciated from Table 2 that, disadvantageously, relatively high voltages are required, e.g., at least about .+-.10V. Providing these high voltages on the same integrated circuit ("IC") chip containing the memory cells adds to fabrication costs and IC chip size. Further, these high potentials are not voltage compatible with the low voltage (e.g., .ltoreq.5V) peripheral devices (or circuits) with which an array of such memory cells will be used. For example, if other circuitry on the IC chip is implemented with CMOS low voltage (.apprxeq.5V) components, it is necessary to protect these lower voltage components and devices against voltage breakdown due to the high voltages required to erase and/or program conventional memory cells. Often such peripheral devices could be designed to operate safely with much lower breakdown voltage margins, but for the inclusion of on-chip flash circuitry.
For example, in fabricating an IC that includes an embedded flash memory and peripheral devices, the fabrication processes for the peripheral devices must be compatible with fabricating the flash memory, e.g., with fabricating higher voltage components. Having to employ two different fabrication technologies to implement higher voltage EPROM or conventional flash memory, and low voltage CMOS (or other low voltage) peripheral devices can reduce yield and add substantially to the manufacturing cost. For example, producing low voltage CMOS (or other) devices might involve twelve masking steps. However, fabricating higher voltage prior art EPROM and flash memory on the same IC will add several additional masking steps.
In addition to its high potential requirements, another inherent limitation in CHE programming is that the cell array may only be implemented as NOR-type, not NAND-type. (See descriptions of FIGS. 3A and 3B later herein.) FIG. 2 depicts an IC 100 that includes an array 110 of memory cells 10, as well as other peripheral circuits and devices necessary to program and/or erase the array. Also indicated in FIG. 2 are wordlines ("WL") that couple control gates 26 of cells 10 in a horizontal row, bitlines ("BL") and sourcelines ("SL") that, respectively, couple drains 16 and sources 14 of cells 10 in a vertical column.
In many applications, the circuitry with which memory cells 10 are used is powered by a single low voltage power supply, e.g., a 1.2V to 5V battery. Unfortunately, as evident from Table 2, it is necessary to step-up these low potential to the high potentials required to erase and/or program the array of cells 10. On-chip positive and negative high voltage pump circuits 130, 140, 145 generate the .+-.10V to .+-.15V (V.sub.Pp, V.sub.Pn) high voltage necessary to program and erase memory cells, and +5V (V.sub.Pm) from a single lower voltage power supply Vdd. A phase generator circuit 125 is also provided to output non-overlapping different phase pulse trains, e.g., .phi.1, .phi.2, .phi.3, .phi.4 to drive the various positive and negative pump circuits.
Because the various pump output voltages are not especially well regulated, voltage regulator circuits 132, 142, 147 are also provided. (An especially interesting approach to providing well regulated potentials to a memory array is described in applicants' co-pending U.S. patent application Ser. No. 08/884,251 filed Jun. 27, 1997 and entitled NODE-PRECISE VOLTAGE REGULATION FOR A MOS MEMORY SYSTEM. Applicants incorporate said application by reference for a more detailed explanation of problems encountered in prior art approaches to erasing and programming conventional memory cells.)
The output voltages from the voltage regulators shown in FIG. 2 will be logically presented to selected groups of cells to provide WL, BL, and SL potentials as required by the various modes of operation, as exemplified by the values shown in Table 2.
From the foregoing discussions of CHE and FN mechanisms, it will be appreciated that the number of cells that can be erased or programmed in parallel, e.g., simultaneously (or in a "flash"), will often be limited by power output provided by the pump circuitry. Clearly, it would be advantageous if the need to provide or generate high erase and/or programming potential were eliminated. Not only would the design and fabrication of peripheral circuitry be eased, but pump or equivalent circuits could be eliminated. The result would be a more reliable, easier to fabricate IC chip that had more area for storage.
Commonly, a horizontal row of cells having their control gates tied-together defined a WL, whereas a vertical column of cells having their drains tied-together define a BL. Source leads in a block of cells are tied-together to define a SL. Changing the WL, BL, SL potential for a selected group of cells enables those cells to be programmed or erased or verified. For ease of illustration, address logic 120 is shown as having a single output lead, but in practice there will be multiple output leads, including leads for Vgs, Vd, and Vs.
In typical arrays, the gate node of cells 10 are coupled to a WL by a polysilicon conductor (e.g., second layer polysilicon or "poly2") since zero DC current will be carried by the WL. The cell drain nodes are coupled to a typically metal BL, and the source nodes are coupled to a SL, typically via an N+ diffusion. Whereas the WL carries zero DC current, the BL may carry a total 5 mA DC if eight cells in the same WL are simultaneously programmed. The eight BLs typically will come from eight respective sub-groups, in which but a single BL is selected from each sub-group. Further, a SL may carry upwards of 5 mA DC current if 64 Kbytes of cells are collectively erased simultaneously. There will typically be a great many SLs, and the SLs may be combined into sub-groups.
The WLs are coupled to a row-selected device by an row decoder (or X-decoder), which for ease of illustration may be assumed to be associated with address logic unit 120 in FIG. 2. The BLs are coupled to a column-selected device driven by a column decoder (or Y-decoder), which is assumed to be associated with address logic 120. The SLs are coupled to source control circuit, assumed to be associated with address logic unit 120. If array 120 includes 1 Mbit of flash memory cells, there will be 1,024 WLs and 1,024 BLs configured in horizontal rows and vertical columns, in which two WLs typically share one SL.
Array 110 may be implemented using different configurations, namely NAND-type flash memory arrays in which F-N tunneling is used to erase and to program, and NOR-type flash memory arrays in which F-N is used to erase, but CHE injection is used to program. Each has its own advantages and disadvantages, as will now be described.
In FIG. 3A, a NOR-type array 160 of memory cells 10 is shown in which drain leads 16 of the individual cells 10 are parallel-coupled using metallized BLs in a so-called NOR-plane. The source leads 14 for the cells are typically grounded, and individual WL signals are coupled to each cell control gate 26.
In FIG. 3A, if a single cell in the NOR-type array is turned-on, the common BL is discharged through that cell to ground. In a read operation, the WL signal to each unselected cell is grounded, and only the selected cell receives a read WL potential. As the resultant function is similar structurally to conventional NOR-logic gates, such arrays are commonly termed NOR-type arrays.
FIG. 3B depicts an alternative array configuration, namely a so-called NAND-type array. In a NAND-type array 170 the metal BL (often termed the main BL) is coupled at a NAND-plane to a number of serially-connected sub-BLs, e.g., SUB-BL1, SUB-BL2, through an upper and a lower sub-BL select transistor, e.g., M1, M2, M3, M4. Typically the upper select transistor is coupled between the main BL and the drain of the top-most cell in the sub-BL. The lower select transistor is coupled between ground and the source of the bottom-most cell in the sub-BL. In a NAND-type array, to read a cell, the select transistors in the associated sub-BL are turned on, and all other select transistors are turned off, thus coupling the main BL only to the sub-BL containing the selected cell. Within the selected sub-BL, the deselected WL potential (which exceeds the Vt of off-state cells) turns on all unselected cells, while the selected cell receives a WL potential intermediate on-state and off-state in magnitude. Whether the main BL is discharged is determined by the Vt state of the selected cell. Since every cell within the sub-BL must be turned on to conduct BL current, this structure logically is similar to a NAND gate, and is termed a NAND-type array.
In comparing NOR-type and NAND-type memory arrays, several trade-offs are seen. NAND-type flash memory cell size is more compact than NOR-type flash memory cell. But a NOR-plane configuration provides higher read current and there is only one selected cell that conducts current from BL to the SL, often ground. By contrast, a NAND-plane configuration has an upper and lower select transistor, and a series of on-cells within the sub-BL that conduct current. This results in higher overall resistance, which decreases the available read current. In fact, the cumulative series-resistance will be so large as to preclude CHE programming. In CHE programming, perhaps 500 .mu.A/cell current is present, and the required a Vds .gtoreq.5V simply cannot be ensured. Thus, NAND-type arrays typically operate more slowly than NOR-type arrays from a given BL potential. For this reason, inexpensive NAND-type arrays find wide use in speech recording devices, in which switching speed may be relatively slow. But the NOR-plane configuration disadvantageously requires a greater cell size to implement than a NAND-plane configuration. Each NOR-plane requires one-half metal contact (shared with an adjacent cell) for a cell to connect to the metal BL. By contrast, the NAND-plane requires only one-half contact (shared with the adjacent sub-BL). Thus, even though a NAND-type array requires an additional upper and lower select pair of transistors per sub-BL, the overall array size is still substantially reduced when compared to a NOR-type configuration. However, as noted above, CHE programming is not compatible with such a configuration.
In summary, there is a need for a system in which programmable flash memory cells may be erased and/or programmed using CMOS-compatible low voltage levels. Preferably such cells should be symmetrical in fabrication so as to permit interchanging source and drain region functions to extend cell endurance lifetime. Further, such cells should be implementable using CMOS technology, without adding more than a few additional process steps. In addition, an array of such cells should be implementable in NAND-type and NOR-type configurations. Finally, such cells should be capable of storing more than two states of data.
The present invention provides such memory cells and a system utilizing such cells.